HD64F36034 datasheet(179/592 Pages) RENESAS

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Section 10 Timer B1

Rev. 4.00 Mar. 15, 2006 Page 147 of 556

REJ09B0026-0400

10.4

Operation

10.4.1

Interval Timer Operation

When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon

reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing

resume immediately. The operating clock of the timer B1 is selected from seven internal clock

signals output by prescaler S, or an external clock input at pin TMB1. The selection is made by

bits TMB12 to TMB10 in TMB1.

After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to

overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to

the CPU.

At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation

(TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1.

10.4.2

Auto-Reload Timer Operation

Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When

a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which

TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input

causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues

from that value. The overflow period can be set within a range from 1 to 256 input clocks,

depending on the TLB1 value.

The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-

reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into

TCB1.

10.4.3

Event Counter Operation

Timer B1 can operate as an event counter in which TMIB1 is set to an event input pin. External

event counting is selected by setting bits TMB12 to TMB10 in TMB1 to 1. TCB1 counts up at

rising or falling edge of an external event signal input at pin TMB1.

When timer B1 is used to count external event input, bit IRQ1 in PMR1 should be set to 1 and

IEN1 in IENR1 should be cleared to 0 to disable IRQ1 interrupt requests.

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