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HD64F36034 Datasheet(PDF) 231 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 231 Page - Renesas Technology Corp |
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231 / 592 page ![]() Section 12 Timer Z Rev. 4.00 Mar. 15, 2006 Page 199 of 556 REJ09B0026-0400 Figure 12.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by GRA_0 compare match are performed by TCNT counters. For details on PWM mode, see section 12.4.5, PWM Mode. GRA_0 Time Synchronous clearing by GRA_0 compare match TCNT values GRA_1 GRB_0 GRB_1 H'0000 FTIOB0 FTIOB1 Figure 12.20 Example of Synchronous Operation |
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