HD64F36034 datasheet(264/592 Pages) RENESAS

Part #	HD64F36034

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

PDF	592 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 232 of 556

REJ09B0026-0400

12.5

Interrupts

There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and

underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while

the corresponding interrupt enable bit is set to 1.

12.5.1

Status Flag Set Timing

IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated

when the GR matches with the TCNT. The compare match signal is generated at the last state of

matching (timing to update the counter value when the GR and TCNT match). Therefore, when

the TCNT and GR matches, the compare match signal will not be generated until the TCNT input

clock is generated. Figure 12.48 shows the timing to set the IMF flag.

IMF

ITMZ

TCNT

TCNT input clock

Compare match

signal

N+1

Figure 12.48 IMF Flag Set Timing when Compare Match Occurs

HD64F36034 Datasheet(PDF) 264 Page - Renesas Technology Corp