HD64F36034 datasheet(273/592 Pages) RENESAS

Part #	HD64F36034

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

PDF	592 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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273 / 592 page

Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 241 of 556

REJ09B0026-0400

Contention between GR Write and Input Capture: If an input capture signal is generated in the

2 state of a GR write cycle, the input capture operation has priority and the write to GR is not

performed. Figure 12.58 shows the timing in this case.

TCNT

GR write cycle

GR address

Input capture

signal

WGR

(internal write signal)

Address bus

GR write data

Figure 12.58 Contention between GR Write and Input Capture

Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits

CMD1 and CMD0 in TFCR are set, note the following:

1. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.

2. Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice

versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the

normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.

HD64F36034 Datasheet(PDF) 273 Page - Renesas Technology Corp