SH7124 datasheet(91/774 Pages) RENESAS

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Section 5 Exception Handling

Rev. 4.00 Jul. 25, 2008 Page 71 of 750

REJ09B0243-0400

Section 5 Exception Handling

5.1

Overview

5.1.1

Types of Exception Handling and Priority

Exception handling is started by four sources: resets, address errors, interrupts and instructions and

have the priority, as shown in table 5.1. When several exceptions are detected at once, they are

processed according to the priority.

Table 5.1

Types of Exceptions and Priority

Exception

Exception Source

Priority

Reset

Power-on reset

High

Manual reset

Interrupt

User break (break before instruction execution)

Address error

CPU address error (instruction fetch)

Instruction

General illegal instructions (undefined code)

Illegal slot instruction (undefined code placed immediately after a

delayed branch instruction*

1 or instruction that changes the PC value*2)

Trap instruction (TRAPA instruction)

Address error

CPU address error (data access)

Interrupt

User break (break after instruction execution or operand break)

NMI

IRQ

On-chip peripheral modules

Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and

BRAF.

2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,

TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.

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