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SH7124 Datasheet(PDF) 26 Page - Renesas Technology Corp |
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SH7124 Datasheet(HTML) 26 Page - Renesas Technology Corp |
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26 / 774 page ![]() Section 1 Overview Rev. 4.00 Jul. 25, 2008 Page 6 of 750 REJ09B0243-0400 1.2 Block Diagram The block diagram of this LSI is shown in figure 1.1. [Legend] ROM: On-chip ROM RAM: On-chip RAM UBC: User break controller H-UDI: User debugging interface INTC: Interrupt controller CPG: Clock pulse generator WDT: Watchdog timer CPU: Central processing unit PFC: Pin function controller MTU2: Multi-function timer pulse unit 2 POE: Port output enable SCI: Serial communication interface CMT: Compare match timer ADC: A/D converter I/O port (PFC) Power- down mode control Peripheral bus (P φ) I bus (B φ) L bus (I φ) Peripheral bus controller SH2 CPU UBC INTC WDT CPG H-UDI MTU2 POE SCI CMT ADC Internal bus controller RAM ROM Figure 1.1 Block Diagram |
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