SH7124 datasheet(129/774 Pages) RENESAS

129 / 774 page

Section 6 Interrupt Controller (INTC)

Rev. 4.00 Jul. 25, 2008 Page 109 of 750

REJ09B0243-0400

Program

execution state

Interrupt?

User break?

I3 to I0

≤

level 14?

Level 14

interrupt?

Level 1

interrupt?

I3 to I0

≤

level 13?

I3 to I0

level 0?

Yes

Save SR to stack

IRQOUT = low

Save PC to stack

Copy interrupt

level to I3 to I0

Read exception

vector table

Branch to exception

handling routine

Yes

Level 15

interrupt?

Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU

IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1).

Therefore,

IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.

When the accepted interrupt is sensed by edge, a high level is output from the

IRQOUT pin at the moment when

the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).

However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted

and has output an interrupt request to the CPU, the

IRQOUT pin holds low level.

The

IRQOUT pin change timing depends on a frequency dividing ratio between the internal (Iφ) and bus (Bφ)

clocks. This flowchart shows that the frequency dividing ratios of the internal (I

φ) and bus (Bφ) clocks are the same.

NMI?

I3 to I0

≤

level 14?

Yes

IRQOUT = high

*1*3

*2*3

Figure 6.3 Interrupt Sequence Flowchart

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