SH7124 datasheet(167/774 Pages) RENESAS

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Section 8 Bus State Controller (BSC)

Rev. 4.00 Jul. 25, 2008 Page 147 of 750

REJ09B0243-0400

Section 8 Bus State Controller (BSC)

The bus state controller (BSC) controls data transmission and reception between the internal buses

(L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, on-

chip RAM, and on-chip peripheral I/O.

8.1

Features

• On-chip FLASH and RAM interface

 32-bit data access per one clock cycle (I φ synchronous)

8.2

Address Map

The address map is listed in table 8.1.

Table 8.1

Address Map

Size

Address

Type of Memory

128 Kbytes

Version

64 Kbytes

Version

32 Kbytes

Version

Bus

Width

H'00000000 to H'00007FFF

32 Kbytes

H'00008000 to H'0000FFFF

64 Kbytes

H'00010000 to H'0001FFFF

On-chip FLASH

128 Kbytes

Reserved

H'00020000 to H'FFFF9FFF

Reserved



H'FFFFA000 to H'FFFFBFFF

On-chip RAM

8 Kbytes

H'FFFFC000 to H'FFFFFFFF

On-chip peripheral

I/O

128 Kbytes

64 Kbytes

8/16

8.3

Access to on-chip FLASH and on-chip RAM

Access to the on-chip FLASH for read is synchronized with I

φ clock and is executed in one clock

cycle. For details on programming and erasing, see section 17, Flash Memory.

Access to the on-chip RAM for read/write is synchronized with I

φ clock and is executed in one

clock cycle. For details, see section 18, RAM.

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