SH7108 datasheet(21/560 Pages) RENESAS

21 / 560 page

Rev.1.00 Sep. 18, 2008 Page xxi of xxxiv

REJ09B0069-0100

Figures

Section 1 Overview

Figure 1.1

Internal Block Diagram of SH7108/SH7106/SH7104/SH7101 .............................

Figure 1.2

Internal Block Diagram of SH7109/SH7107/SH7105............................................

Figure 1.3

SH7108/SH7106/SH7104/SH7101 Pin Assignment ..............................................

Figure 1.4

SH7109/SH7107/SH7105 Pin Assignment ............................................................

Section 2 CPU

Figure 2.1

CPU Internal Registers ........................................................................................... 16

Figure 2.2

Data Format in Registers ........................................................................................ 19

Figure 2.3

Data Formats in Memory ....................................................................................... 19

Figure 2.4

Transitions between Processing States ................................................................... 42

Section 3 MCU Operating Modes

Figure 3.1

Address Map of SH7108 ........................................................................................ 48

Figure 3.2

Address Map of SH7106 ........................................................................................ 49

Figure 3.3

Address Map of SH7104 ........................................................................................ 50

Figure 3.4

Address Map of SH7101 ........................................................................................ 51

Figure 3.5

Address Map for Operating Modes of SH7109...................................................... 52

Figure 3.6

Address Map for Operating Modes of SH7107...................................................... 53

Figure 3.7

Address Map for Operating Modes of SH7105...................................................... 54

Section 4 Clock Pulse Generator

Figure 4.1

Block Diagram of the Clock Pulse Generator ........................................................ 55

Figure 4.2

Connection of the Crystal Resonator (Example) .................................................... 56

Figure 4.3

Crystal Resonator Equivalent Circuit ..................................................................... 56

Figure 4.4

Example of External Clock Connection ................................................................. 57

Figure 4.5

Cautions for Oscillator Circuit System Board Design............................................ 58

Figure 4.6

Recommended External Circuitry Around the PLL ............................................... 58

Section 6 Interrupt Controller (INTC)

Figure 6.1

INTC Block Diagram ............................................................................................. 74

Figure 6.2

Control of IRQ3 to IRQ0 Interrupts ....................................................................... 83

Figure 6.3

Interrupt Sequence Flowchart................................................................................. 88

Figure 6.4

Stack after Interrupt Exception Processing ............................................................ 89

Figure 6.5

Example of the Pipeline Operation when an IRQ Interrupt Is Accepted................ 91

Section 7 Bus State Controller (BSC)

Figure 7.1

BSC Block Diagram............................................................................................... 94

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