SH7713 datasheet(554/904 Pages) RENESAS

554 / 904 page

Section 15 Realtime Clock (RTC)

Rev.1.50 Aug. 30, 2006 Page 514 of 860

REJ09B0288-0150

15.3.9

Second Alarm Register (RSECAR)

RSECAR is an alarm register corresponding to the second counter RSECCNT of the RTC. When

the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among

RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register

comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if

each of those coincide, an RTC alarm interrupt is generated.

The range of second alarm which can be set is 0 to 59 (decimal). Errant operation will result if any

other value is set.

RSECAR is an 8-bit readable/writable register. The ENB bit in RSECAR is initialized to 0 by a

power-on reset. The remaining RSECAR fields are not initialized by a power-on reset or manual

reset, or in standby mode.

Bit

Bit Name

Initial Value

R/W

Description

ENB

R/W

Second Alarm Enable

Specifies whether comparison of RSECCNT and

RSECAR is performed as an alarm condition.

0: Not compared

1: Compared

6 to 4



R/W

Setting value for 10-unit of second alarm in the

BCD-code.

The range can be set from 0 to 5 (decimal).

3 to 0



R/W

Setting value for 1-unit of second alarm in the

BCD-code.

The range can be set from 0 to 9 (decimal).

15.3.10

Minute Alarm Register (RMINAR)

RMINAR is an alarm register corresponding to the minute counter RMINCNT. When the ENB bit

is set to 1, a comparison with the RMINCNT value is performed. From among

RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR, the counter and alarm register

comparison is performed only on those with ENB bits and the YAEN bit in RCR3 set to 1, and if

each of those coincide, an RTC alarm interrupt is generated.

The range of minute alarm which can be set is 0 to 59 (decimal). Errant operation will result if any

other value is set.

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