SH7713 datasheet(571/904 Pages) RENESAS

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Section 16 Serial Communication Interface with FIFO (SCIF)

SCIS3C3A_000020020900

Rev.1.50 Aug. 30, 2006 Page 531 of 860

REJ09B0288-0150

Section 16 Serial Communication Interface with FIFO

(SCIF)

This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial

Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock

synchronous serial communication.

The SCIF provides a 16-stage FIFO register for both transmission and reception, enabling fast,

efficient, and continuous communication.

16.1

Features

The SCIF features are listed below.

• Asynchronous mode

Serial data communication is executed using an asynchronous system in which

synchronization is achieved character by character. Serial data communication can be carried

out with standard asynchronous communication chips such as a Universal Asynchronous

Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).

There is a choice of 8 serial data communication formats.

Data length: 7 or 8 bits

Stop bit length: 1 or 2 bits

Parity: Even/odd/none

Receive error detection: Parity, framing, and overrun errors

Break detection: If a framing error is following by at least one frame at the space “0” (low)

level, a break is detected.

• Clock synchronous mode

Serial data communication is synchronized with a clock. Serial data communication can be

carried out with other chips that have a synchronous communication function.

Data length: 8 bits

Receive error detection: Overrun error

• Full-duplex communication capability

The transmitter and receiver are independent units, enabling transmission and reception to be

performed simultaneously.

The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and

continuous serial data transmission and reception.

• On-chip baud rate generator allows any bit rate to be selected.

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