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SH7713 Datasheet(PDF) 579 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 579 Page - Renesas Technology Corp |
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579 / 904 page  Section 16 Serial Communication Interface with FIFO (SCIF) Rev.1.50 Aug. 30, 2006 Page 539 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 4 O/ E 0 R/W Parity Mode Selects either even or odd parity for use in parity addition and checking. The O/ E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking in asynchronous mode. The O/ E bit setting is invalid in clock synchronous mode, and when parity addition and checking is disabled in asynchronous mode. 0: Even parity* 1 1: Odd parity* 2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. |
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