SH7713 datasheet(583/904 Pages) RENESAS

583 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 543 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Receive Enable

Enables or disables the start of serial reception by the

SCIF.

0: Reception disabled*

1: Reception enabled*

Notes: 1. Clearing the RE bit to 0 does not affect

the DR, ER, BRK, RDF, FER, PER, and

ORER flags, which retain their state.

2. SCSMR and SCFCR settings must be

made, the receive format decided, and the

receive FIFO reset, before the RE bit is

set to 1.

REIE

R/W

Receive Error Interrupt Enable

Enables or disables generation of receive-error

interrupt (ERI) request and break interrupt (BRI)

request. The REIE bit setting is available when the

RIE bit is cleared to 0.

0: Receive-error interrupt (ERI) request and break

interrupt (BRI) request disabled*

1: Receive-error interrupt (ERI) request and break

interrupt (BRI) request enabled

Note: *

A receive-error interrupt (ERI) request and

break interrupt (BRI) request can be cleared

by reading 1 from the ER, BRK, and ORER

flags, then clearing the flags to 0, or by

clearing the RIE and REIE bits to 0.

Even if the RIE bit is cleared to 0, setting

the REIE bit to 1 enables generation of the

ERI and BRI requests. This setting is

achieved to notify the ERI and BRI requests

to the interrupt controller at the DMAC

transfer.



Reserved

This bit is always read as 0. The write value should

always be 0.

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