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SH7713 Datasheet(PDF) 585 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 585 Page - Renesas Technology Corp |
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585 / 904 page ![]() Section 16 Serial Communication Interface with FIFO (SCIF) Rev.1.50 Aug. 30, 2006 Page 545 of 860 REJ09B0288-0150 16.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The lower 8 bits specify the status flags that indicate the SCIF operating status. The upper 8 bits indicate the receive error number of data in the receive-FIFO register. SCFSR can be read or written to by the CPU at all times. However, 1 cannot be written to the ER, TEND, TDFE, BRK, RDF, and DR flags. Also note that in order to clear these flags to 0, they must be read as 1 beforehand. The FER and PER flags are read-only flags and cannot be modified. SCFSR is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state, and retains its contents. Bit Bit Name Initial Value R/W Description 15 14 13 12 PER3 PER2 PER1 PER0 0 0 0 0 R R R R Parity Error Number 3 to 0 Indicate the number of data bytes, in which parity errors are generated, in receive data stored in SCFRDR. After setting the ER bit in SCFSR, the values of bits 15 to 12 indicate the number of parity error generated data. When all 16 bytes of receive data in SCFRDR has parity errors, the PER3 to PER0 bits indicate 0. 11 10 9 8 FER3 FER2 FER1 FER0 0 0 0 0 R R R R Framing Error Number 3 to 0 Indicate the number of data bytes, in which framing errors are generated, in receive data stored in SCFRDR. After setting the ER bit in SCFSR, the values of bits 11 to 8 indicate the number of framing error generated data. When all 16 bytes of receive data in SCFRDR has framing errors, the FER3 to FER0 bits indicate 0. |
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