SH7713 datasheet(581/904 Pages) RENESAS

581 / 904 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev.1.50 Aug. 30, 2006 Page 541 of 860

REJ09B0288-0150

16.3.6

Serial Control Register (SCSCR)

SCSCR performs enabling or disabling of the SCIF transfer operations and interrupt requests, and

selection of the serial clock source.

SCSCR can be read or written to by the CPU at all times.

SCSCR is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby

mode or in the module standby state, and retains its contents.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TIE

R/W

Transmit Interrupt Enable

Enables or disables generation of a transmit-FIFO-

data-empty interrupt (TXI) request when the TDFE

flag in SCFSR is set to 1 after the serial transmit data

is transferred from SCFTDR to SCTSR and the

number of data bytes in the transmit FIFO register is

equal to or below the trigger set number.

0: Transmit-FIFO-data-empty interrupt (TXI) request

disabled*

1: Transmit-FIFO-data-empty interrupt (TXI) request

enabled

Note: *

TXI interrupt requests can be cleared by

writing transmit data exceeding the transmit

trigger set number to SCFTDR, reading 1

from the TDFE flag, then clearing it to 0, or

by clearing the TIE bit to 0.

SH7713 Datasheet(PDF) 581 Page - Renesas Technology Corp