7721 datasheet(338/577 Pages) RENESAS

338 / 577 page

13-59

DMA CONTROLLER

13.5 Single transfer mode

7721 Group User’s Manual

13.5.2 Operation in single transfer mode

Figure 13.5.5 shows the operation flowchart of the single transfer mode, and Figure 13.5.6 shows a timing

diagram of the single transfer mode (burst transfer mode).

For the cycle-steal transfer mode, refer to the following:

• All transfers except for the last 1-unit transfer: Figure 13.8.12

• Last 1-unit transfer: Figure 13.8.14

Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer.

DMAi request bit

← 0

1-unit transfer

Transfer completion of

1 block ?

TC “L” output (Note)

DMAi interrupt request bit

← 1

DMAi enable bit

← 0

(Only in cycle-steal transfer mode)

(Refer to section “13.4 Operation.”)

Note: When TC pin validity bit is “1”

Burst·Edge

: In burst transfer mode (edge sense)

Burst·Level·L

: In burst transfer mode (level sense) with DMAREQi pin’s input level = L

Burst·Level·H

: In burst transfer mode (level sense) with DMAREQi pin’s input level = H

Cycle-steal·Requested

: In cycle-steal transfer mode with any request of DMA0–3

Cycle-steal·No request

h no request of DMA0–3

DMAi request bit

← 0

(Only burst·edge)

DMAi request bit ?

Burst·Level·H

Cycle-Steal·No request

Burst·Edge

Burst·Level·L

Cycle-steal·Requested

Fig. 13.5.5 Operation flowchart of single transfer mode

: In cycle-steal transfer mode wit

7721 Datasheet(PDF) 338 Page - Renesas Technology Corp

7721 Datasheet(HTML) 338 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL