| Electronic Components Datasheet Search |
|
7721 Datasheet(PDF) 334 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7721 Datasheet(HTML) 334 Page - Renesas Technology Corp |
|
334 / 577 page ![]() 13-55 DMA CONTROLLER 13.5 Single transfer mode 7721 Group User’s Manual b7 b0 b15 b8 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Functions Bit At reset RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to “00000016” to “FFFFFF16.” [Read] The read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Functions Bit At reset RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to “00000016” to “FFFFFF16.” [Read] The read value indicates the destination address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0 b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Functions Bit At reset RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to “00000116” to “FFFFFF16.” [Read] The read value indicates remaining byte number of the transfer data. Undefined RW Note: When writing to this register, write to all 24 bits. Do not set this register to “00000016.” b23 b16 Fig. 13.5.1 Register structures of SARi, DARi, and TCRi in single transfer mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |