7721 datasheet(333/577 Pages) RENESAS

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13-54

DMA CONTROLLER

13.5 Single transfer mode

7721 Group User’s Manual

13.5 Single transfer mode

This mode is used to transfer a block of data once.

Table 13.5.1 lists the specifications of the single transfer mode, and Figure 13.5.1 shows the register

structures of SARi, DARi, and TCRi in this mode.

Table 13.5.1 Specifications of single transfer mode

Performance specifications

Not required.

TCRi = 0

___

q Falling edge of the TC pin’s input from “H” to “L”

___

(when the TC pin validity bit =“1”)

q Write “0” to the DMAi enable bit

At normal termination

SARi latch: Indicates the transfer start address of data block at the

transfer source.

SARi: Indicates the address of the next transfer source.

DARi latch: Indicates the transfer start address of data block at the

transfer destination.

DARi: Indicates the address of the next transfer destination.

TCRi latch: Indicates the number of transfer bytes.

TCRi: Indicates the number of remaining transfer bytes.

Item

Transfer parameter memory

Condition of normal termination

Conditions of forced termination

Interrupt request generation timing

Functions of registers

___

pin validity bit: Bit 1 at address 6816

7721 Datasheet(PDF) 333 Page - Renesas Technology Corp