 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
7721 Datasheet(PDF) 329 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7721 Datasheet(HTML) 329 Page - Renesas Technology Corp |
|
|
329 / 577 page  7721 Group User’s Manual 13-50 DMA CONTROLLER 13.4 Operation [Precautions for burst transfer mode] 1. In the burst transfer mode (edge sense), the DMAi request bit is cleared to “0” when the transfer of an entire batch of data is complete or the transfer is forced into termination. Therefore, another DMA request of the same channel i is invalid if generated during DMAi transfer. Fig. 13.4.10 Timing when clearing DMAi request bit to “0” in burst transfer mode 2. Because interrupt priority levels are determined while the CPU fetches an operation code, interrupt requests are not accepted during a DMA transfer. In the burst transfer mode (edge sense), therefore, interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination. E Transition of right to use bus (from DMAC to CPU) 1-unit transfer Termination processing DMAi request bit is set to “0.” |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
