7721 datasheet(327/577 Pages) RENESAS

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7721 Group User’s Manual

13-48

DMA CONTROLLER

13.4 Operation

13.4.3 Burst transfer mode

The burst transfer mode can operate in either edge sense or level sense mode.

(1)

Burst transfer mode (edge sense)

When the transfer mode select bit = “0” and the edge sense/level sense select bit = “0,” this mode

is selected. (Refer to “Figures 13.2.6 and 13.2.8.”)

In this mode, all of the DMA request sources are available.

Figure 13.4.8 shows a transfer example in the burst transfer mode (edge sense).

When once a DMA request is accepted in this mode, an entire batch of data is transferred: the right

to use bus is not returned to the CPU until the transfer is complete.

During a burst transfer, any DMA request (including that of other channels) cannot be accepted.

However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer.

(Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time,

the right to use bus is not returned to the CPU, and the request is accepted.

When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to use bus

to the CPU. When the next DMA request is generated, the right is once returned to the CPU to

sample the DMA request.

(2)

Burst transfer mode (level sense)

When the transfer mode select bit = “0” and the edge sense/level sense select bit = “1 ,” this mode

is selected. (Refer to “Figures 13.2.6 and 13.2.8.”)

In this mode, only the external source is used as a DMA request source. Set the DMA request source

select bits to “00012.” (Refer to “Figure 13.2.8.”)

Figure 13.4.9 shows a transfer example in the burst transfer mode (level sense).

_________

When the DMAREQi pin’s input level = “L,” the DMAi request bit is cleared to “0”; when this pin’s input

level = “L,” the DMAi request bit is set to “1.”

_________

Therefore, when the DMAREQi pin’s input level is “L” with the DMAi enable bit = “1,” a DMA transfer

_________

starts. When the DMAREQi pin’s input level goes from “L” to “H,” the right to use bus will be returned

_________

to the CPU at completion of 1-unit transfer under execution at that time. When the DMAREQi pin’s

input level goes “L” again, the DMA transfer restarts at the next address.

Once a DMAi transfer starts, any DMA request (including that of other channels) cannot be accepted,

_________

even if the DMAREQi pin’s input level is “H,” until the transfer is terminated normally or forcibly.

However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer.

(Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time,

the right to use bus is not returned to the CPU, and the request is accepted.

When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to the CPU.

If the next DMA request is generated, the right is once returned to the CPU to sample the DMA

request.

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