7721 datasheet(326/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-47

13.4 Operation

[Precautions for 1-bus cycle transfer]

1. The area that overlaps with internal RAM and SFRs must not be assigned to an external memory.

When the contents in the overlapped area are read, the data of internal RAM or SFRs and that of external

memory are simultaneously placed on the data bus; and they collide with each other.

2. For the system that transfers data with 16-bit external data bus width from an external memory to an

8-bit I/O, the external memory must be composed to be read in a unit of 8 bits.

If the external memory cannot be read in a unit of 8 bits, the data read from the external memory at data

copy collides with the copied data on the data bus.

3. Under the following conditions, 1-bus cycle transfer cannot be performed. (Refer to “Table 13.4.5.”):

q External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Fixed or

Forward, Data’s start address of memory = Odd

q External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Backward,

Data’s start address of memory = Even

q External data bus width = 16 bits, Transfer unit = 16 bits, Target memory of DMA transfer = DRAM

area, Address direction of memory = Backward, Data’s start address of memory = Odd

q External data bus width = 8 bits, Transfer unit = 16 bits

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