7721 datasheet(322/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-43

13.4 Operation

External data

bus width

I/O

connection

Transfer

unit

Read/Write address

of memory

Data flow

16 bits

Data bus

D0–D7

and

D8–D15

Even address

and

Odd address

Even address

M37721

Memory

I/O

Data bus D8–D15

Data bus D0–D7

M37721

I/O

M37721

I/O

M37721

(Note)

Note: Data is copied from data bus D0–D7 to D8–D15 or from data bus D8–D15 to

D0–D7 in the M37721’s DMAC. Note the data copy delay time td(data).

M37721

16 bits

8 bits

Memory

Data bus D8–D15

Data bus D0–D7

Data bus D8–D15

Data bus D0–D7

Odd address

I/O

Memory

16 bits

8 bits

Data bus

D0–D7

Data bus

D8–D15

Even address

Odd address

(Note)

Memory

I/O

Data bus D8–D15

Data bus D0–D7

Note: Data is copied from data bus D0–D7 to D8–D15 or from data bus D8–D15 to

D0–D7 in the M37721’s DMAC. Note the data copy delay time td(data).

Data bus D8–D15

Data bus D0–D7

Memory

8 bits

Data bus

D0–D7

Data bus D0–D7

I/O

Memory

Even address

and

Odd address

Note: When the memory is the internal memory or SFR, the above case for external data bus width = 16 bits

applies.

Table 13.4.6 Data flows on data bus in 1-bus cycle transfer

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