7721 datasheet(323/577 Pages) RENESAS

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7721 Group User’s Manual

13-44

DMA CONTROLLER

13.4 Operation

External

data bus

width

I/O

connection

Transfer

unit

Read/Write

address of

memory

Output of address bus, data bus, and bus control signals

16 bits

Data bus

D0–D7

and

D8–D15

Data bus

D8–D15

8 bits

Even

address

and

Odd address

: When the memory is the internal memory or SFR, data is output. When the memory is the external

memory, it enters a floating state.

A8/D8–A15/D15

A16/D0–A23/D7

BLE

BHE

Transfer source

address

Odd address

data

A8/D8–A15/D15

A16/D0–A23/D7

BLE

BHE

Invalid data

BLE

BHE

Odd address data

Copy

BLE

BHE

BLE

BHE

Data

R/W

Transferred from memory to I/O

Invalid data

I/O data

Transferred from I/O to memory

16 bits

Transfer source

address

Even address

data

Transfer destination

address

Transfer destination

address

16 bits

8 bits

Data bus

D0–D7

Even

address

Odd

address

Transfer source

address

Transfer source

address

Even address

data

Transfer destination

address

Transfer destination

address

A8/D8–A15/D15

A16/D0–A23/D7

Transfer source

address

Transfer source

address

Transfer destination

address

Transfer destination

address

Copy

Transfer destination

address

Transfer destination

address

Copy

I/O data

A8/D8–A15/D15

A16/D0–A23/D7

Transfer source

address

Transfer source

address

Copy

Even address

data

Even

address

Odd

address

A8/D8–A15/D15

A16/D0–A23/D7

Transfer source

address

Transfer source

address

Odd address data

Invalid data

Transfer destination

address

Transfer destination

address

8 bits

Data bus

D0–D7

Even

address

and

Odd address

A8–A15

A16/D0–A23/D7

Transfer source address

Transfer source

address

Transfer destination address

Transfer destination

address

Table 13.4.7 Outputs of address bus, data bus, and bus control signals in 1-bus cycle transfer

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