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7721 Datasheet(PDF) 319 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 319 Page - Renesas Technology Corp |
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319 / 577 page ![]() 7721 Group User’s Manual 13-40 DMA CONTROLLER 13.4 Operation (1) Register operation in 1-bus cycle transfer Figure 13.4.6 shows a basic operation of registers for 1-unit transfer in 1-bus cycle transfer. For register values to be specified, refer to section “13.5 Single transfer mode” through section “13.8 Link array chain transfer mode.” It is because these values vary depending on each continuous transfer mode. In 1-bus cycle transfer, a read and write of 1-transfer-unit data are simultaneously performed during 1-bus cycle. Fig. 13.4.6 Basic operation of registers for 1-unit transfer in 1-bus cycle transfer Transfer source address is specified by DARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is “0,” transfer of 1 data block is terminated. Contents of DARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from I/O and is written to memory simultaneously (R/W = L level). Transfer source address is specified by SARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is “0,” transfer of 1 data block is terminated. Contents of SARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from memory and is written to I/O simultaneously (R/W = H level). qWhen transferring from memory to I/O SARi SARi latch DMA latch DMAC Memory (Transfer source) DMAC I/O DMAACKi I/O DARi DARi latch TCRi TCRi latch (Transfer destination) Incrementer/ Decrementer Decrementer qWhen transferring from I/O to memory Memory SARi SARi latch DMA latch DMAACKi DARi DARi latch TCRi TCRi latch Incrementer/ Decrementer Decrementer (Transfer source) (Transfer destination) V When the transfer unit is 16 bits, the incrementer/decrementer and the decrementer increment or decrement by 2. Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi, and TCRi are used.) |
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