7721 datasheet(320/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-41

13.4 Operation

(2)

Bus operation in 1-bus cycle transfer

The time required for 1-unit transfer in 1-bus cycle transfer is given by the following formulas:

• Transfer from memory to I/O: Transfer time per 1-unit transfer = (Read cycle of memory)

• Transfer from I/O to memory: Transfer time per 1-unit transfer = (Write cycle of memory)

In 1-bus cycle transfer, 1-transfer-unit data is accessed in 1-bus cycle, so that limitations are imposed

on the transfer conditions to be applied. Table 13.4.5 lists the conditions of 1-bus cycle transfer and

the transfer time per 1-unit transfer, and Figure 13.4.7 shows the bus-cycle operation waveforms in

1-bus cycle transfer.

Table 13.4.5 Conditions of 1-bus cycle transfer and Transfer time per 1-unit transfer

Transfer

unit

16 bits

8 bits

16 bits

8 bits

External

bus width

16 bits

(including

internal

bus)

8 bits

Address directions

Fixed/Forward

Backward

Fixed/Forward/

Backward

Fixed/Forward/

Backward

Fixed/Forward/

Backward

Even

Odd

Even

Odd

Even/Odd

Data’s start

address

Read/Write cycle (Unit:

φ cycle)

Formula

1 + i

2 + i

1 + i

No Wait

2 (a)

3 (b)

2 (a)

With Wait

3 (c)

DRAM area

4 (d)

Address directions: Refer to section “13.4.2 (3) Address directions in 1-bus cycle transfer.”

There is no address direction on the I/O side.

i: A term of E = ‘L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”.

When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended

by Ready must be added.

( ): Indicates the corresponding waveform in Figure 13.4.7.

/: 1-bus cycle transfer cannot be performed.

When the external data bus width = 16 bits and the transfer unit = 8 bits are selected, the data bus

which the memory uses and the data bus to which I/O is connected may be different. In such a case,

data is copied from the data bus of a transfer source to that of a transfer destination by using the

DMA latch. For the combination that data copy may occur, data copy delay time td(data) must be taken

into consideration.

Table 13.4.6 lists the data flows on the data bus in 1-bus cycle transfer, and Table 13.4.7 lists the

outputs of the address bus, the data bus, and the bus control signals in 1-bus cycle transfer.

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