7721 datasheet(324/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-45

13.4 Operation

(3)

Address directions in 1-bus cycle transfer

In 1-bus cycle transfer, the transfer source and destination address directions of memory are selectable.

(Refer to “Figure 13.2.6.”) Addresses move in the specified direction by the transfer unit.

Tables 13.4.8 and 13.4.9 list address directions in 1-bus cycle transfer and examples of transfer

results.

Table 13.4.8 Address directions in 1-bus cycle transfer and examples of transfer results (1)

Fixed

—

Forward

—

Backward

—

Data

Low order

Data

Transfer unit : 8 bits

Address direction

Transfer

source

memory

Transfer unit : 16 bits

Transfer

sequence

External data bus width : 16 bits

Transfer

destination

I/O

Data arrangement

on transfer source

memory

Data arrangement

on transfer source

memory

Transfer destination

I/O

Transfer

sequence

External data bus width : 16 bits or 8 bits

Transfer destination

I/O

High order

Low order

High order

Data 1

Low order

High order

Data 2

Low order

High order

Data 3

Low order

High order

Data

1–3

Low order

High order

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1–6

Data 3

Data 2

Data 1

Low order

High order

Low order

High order

Low order

High order

Data

1–3

Low order

High order

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 1–6

V : Transfer start

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