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7721 Datasheet(PDF) 328 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 328 Page - Renesas Technology Corp |
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328 / 577 page  DMA CONTROLLER 7721 Group User’s Manual 13-49 13.4 Operation CPU DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DRAM refresh DMA1 CPU DMA0 CPU This example applies on the following conditions: • Channel priority level: Fixed (Channel 0 > Channel 1) DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DRAM refresh DMA1 CPU DMA0 CPU Channel 1 This example applies on the following conditions: • Both of DMA0 and DMA1 request sources are external sources. • Channel priority level: Fixed (Channel 0 > Channel 1) Entire data transfer Entire data transfer Channel 0 Fig. 13.4.8 Transfer example in the burst transfer mode (edge sense) Fig. 13.4.9 Transfer example in the burst transfer mode (level sense) Channel 1 Entire data transfer Entire data transfer Channel 0 |
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