7721 datasheet(332/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-53

13.4 Operation

2. When a DMA transfer of another channel is subsequently performed

In the cycle-steal transfer mode, it takes 1.5 cycles of

φ from the generation of a DMA request until that

of a BUS REQUEST (DMAC).

Therefore, if a DMA request of another channel is generated during a DMAi transfer in the cycle-steal

mode, either one of the following two cases occurs depending on its timing of request generation:

• The DMAC performs the DMA transfer subsequently without returning the right to use bus.

• After returning the right to use bus to the CPU once, the DMAC regains the right and performs the

DMA transfer.

Fig. 13.4.13 Conditions for performing DMA transfers of another channel subsequently

Bus request

sampling

1-unit transfer

When a DMA request is generated at the following timing, it is not in time to the next bus request sampling (V).

Therefore, DMAC returns the right to use bus to the CPU. Then, the DMAC regains the right and restarts DMA transfer.

• Except for the last 1-unit transfer is selected without Wait. In addition, a time of 0.5 cycle of

φ is less than tsu(DRQ – φ1).

(V)

DMA transfer is subsequently performed if DMAi

request bit of another channel becomes “1” during

this term (on condition that DMAi request bit of

another channel becomes “1” at the timing

satisfying tsu(DRQ –

φ1)).

After returning the right to use bus to

CPU once, DMAC regains the right and

restarts DMA transfer if DMAi request

bit of another channel becomes “1”

during this term.

7721 Datasheet(PDF) 332 Page - Renesas Technology Corp