7721 datasheet(331/577 Pages) RENESAS

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7721 Group User’s Manual

13-52

DMA CONTROLLER

13.4 Operation

[Precautions for cycle-steal transfer mode]

1. When DMA transfers of the same channel are continuously performed

In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” in every 1-unit transfer. Also, it

takes 1.5 cycles of

φ from the generation of a DMA request until that of a BUS REQUEST (DMAC).

Therefore, if another DMA request of the same channel i is generated during a DMAi transfer in the cycle-

steal transfer mode, any one of the following three cases occurs depending on the timing of request

generation:

• The DMA request becomes invalid.

• The DMA transfer continues without returning the right to use bus.

• After returning the right to use bus to the CPU, the DMAC regains the right and restarts the DMA

transfer.

Fig. 13.4.12 Conditions for performing DMA transfers of the same channel continuously

1-unit transfer

DMA transfers are

continuously performed if

DMAi request bit becomes “1”

during this term (on condition

that DMAi request bit

becomes “1” at the timing

satisfying tsu(DRQ –

φ1)).

After returning the right to use bus

to CPU, DMAC regains the right and

restarts DMA transfer if DMAi request

bit becomes “1” during this term.

When a DMAi request is generated at the following timings, it is not in time to the next bus request sampling (V).

Therefore, DMAC returns the right to use bus to the CPU. Then, DMAC regains the right and restarts the DMA transfer.

• Except for the last 1-unit transfer, 1-bus cycle transfer is selected without Wait.

• Except for the last 1-unit transfer, 1-bus cycle transfer is selected with Wait. In addition, a time of 0.5 cycle of

φ is

less than tsu(DRQ –

φ1).

DMAi request is invalid

even when DMAi request

bit becomes “1.”

Bus request

sampling

(V)

DMAi request bit is cleared to

“0” during this term.

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