7721 datasheet(330/577 Pages) RENESAS

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DMA CONTROLLER

7721 Group User’s Manual

13-51

13.4 Operation

13.4.4 Cycle-steal transfer mode

When the transfer mode select bit = “1” and the edge sense/level sense select bit = “0,” this mode is

selected. (Refer to “Figures 13.2.6 and 13.2.8.”)

In this mode, all of the DMA request sources are available.

Figure 13.4.11 shows a transfer example in the cycle-steal transfer mode

1-transfer-unit data is transferred for each DMA request.

The BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to “Table

13.2.3.”) When a DRAM refresh request or Hold request is generated at this time, the right to use bus is

not returned to the CPU, and the request is accepted. When several DMA requests are generated, the

request of the channel which has the highest priority among them is accepted, and DMA transfer is

performed without returning the right to use bus to the CPU. When any request is not generated, the CPU

gains the right.

CPU DMA1

DRAM

refresh

CPU

DMA0

DMA1 DMA0

DMA1

DMAREQ0

DMA0 request bit

DMA0 enable bit

DMAREQ1

DMA1 request bit

DMA1 enable bit

DRAM refresh request

Right to use bus

This example applies on the following conditions:

• Both of DMA0 and DMA1 request sources are external sources

• Channel priority level: Fixed (Channel 0 > Channel 1)

Fig. 13.4.11 Transfer example in cycle-steal transfer mode

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