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7721 Datasheet(PDF) 318 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 318 Page - Renesas Technology Corp |
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318 / 577 page  DMA CONTROLLER 7721 Group User’s Manual 13-39 13.4 Operation In 1-bus cycle transfer, the following considerations must be taken in designing the system: • Achieve the condition that 1-transfer-unit data can be accessed in 1-bus cycle. (Refer to “Table 13.4.5.”) • Specify the transfer address direction and I/O connections. (Refer to “Figure 13.2.7.”) • Compose the read and write signal generating circuit externally. (These signals are for I/Os.) The M37721 outputs signals to the memory. Accordingly, make sure to compose the circuit which generates write signals for I/Os when the M37721 outputs read signals; which generates read signals for I/Os when the M37721 outputs write signals. Figure 13.4.5 shows an example of the circuit generating a write signal and a read signal for I/Os. M37721 R/W DMAACKi DMAREQi E Read Write I/O Generating circuit for read and write signals to I/Os DMA acknowledge DMA request Fig. 13.4.5 Example of circuit generating write signal and read signal for I/Os |
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