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13-61

DMA CONTROLLER

13.6 Repeat transfer mode

7721 Group User’s Manual

13.6 Repeat transfer mode

This mode is used to transfer one block of data repeatedly. Table 13.6.1 lists the specifications of the repeat

transfer mode, and Figure 13.6.1 shows the register structures of SARi, DARi, and TCRi in this mode.

Table 13.6.1 Specifications of repeat transfer mode

Item

Transfer parameter memory

Condition of normal termination

Conditions of forced termination

Interrupt request generation timing

Functions of registers

Performance specifications

Not required

— (No normal termination)

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q Falling edge of the TC pin’s input from “H” to “L”

___

(when the TC pin validity bit = “1”)

q Write “0” to the DMAi enable bit

No request is generated.

SARi latch: Indicates the transfer start address of data block at the

transfer source.

SARi: Indicates the address of the next transfer source.

DARi latch: Indicates the transfer start address of data block at the

transfer destination.

DARi: Indicates the address of the next transfer destination.

TCRi latch: Indicates the number of transfer bytes.

TCRi: Indicates the number of remaining bytes being transferred.

___

pin validity bit: Bit 1 at address 6816

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