7721 datasheet(565/577 Pages) RENESAS

565 / 577 page

7721 Group User’s Manual

17–102

APPENDIX

Appendix 11. Electrical characteristics

Destination

address

Source address

Address

Data

td( 1-STi)

td(AL-E)

td(AM-E)

th(ALE-AM)

td(E-DHQ)

td(E-DLQ)

td(ALE-E)

tw(ALE)

td(R/W-E)

td(AH-E)

th(ALE-AH)

th(E-R/W)

tsu(TCIN)

td( 1-DAK)

tw(TCIN)

th(E-AL)

th(E-AM)

When DMA transfer is forcedly completed by TC input

•TC input timing

ALE output

R/W output

A0–A7 output

A8/D8–A15/D15 output

(BYTE = “L”)

A16/D0–A23/D7 output

Test conditions

•Vcc = 5 V ± 10 %

•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V

•D0–D15 input : VIL = 0.8 V, VIH = 2.5 V

•TC input : VIL = 0.8 V, VIH = 2.5 V

DMAACKi

TC input

ST0

A8/D8–A15/D15 output

(BYTE = “H”)

Destination

address

Destination address

Address

Data

Source address

Destination

address

Source

address

Destination

address

Source

address

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