7721 datasheet(569/577 Pages) RENESAS

569 / 577 page

7721 Group User’s Manual

17–106

APPENDIX

Appendix 11. Electrical characteristics

Fig. 13 Test circuit for each pin

___

Fig. 14 Test circuit for TC output delay time and

___

TC output pulse width

A0/MA0–A7/MA7

A8/D8–A15/D15

A16/D0–A23/D7

P10

100 pF

3 k

Ω

Table 6 Calculation formulas for DMA transfer bus timing

depending on f(XIN) (Vcc = 5 V ± 10 %, Vss = 0 V,

Ta = –20 to 85 °C)

td(AL–E)

td(AM–E)

td(AH–E)

tw(ALE)

td(BLE–E)

td(BHE–E)

td(R/W–E)

th(E–AL)

th(E–AM)

th(E–DLQ)

th(E–DHQ)

tpzx(E–DLZ)

tpzx(E–DHZ)

th(E–BLE)

th(E–BHE)

th(E–R/W)

tw(EL)

tw(TC)

Symbol

Unit

1 ! 109

f(XIN)

1 ! 109

f(XIN)

1 ! 109

f(XIN)

1 ! 109

f(XIN)

1 ! 109

f(XIN)

1 ! 109

f(XIN)

2 ! 109

f(XIN)

4 ! 109

f(XIN)

2 ! 109

f(XIN)

– 25

– 18

– 20

– 22

– 25

– 22

– 20

– 25

– 30

f(XIN)

1 ! 109

Transfer source/Transfer

destination wait bit = “1”

Transfer source/Transfer

destination wait bit = “0”

Calculation formula

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