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7721 Datasheet(PDF) 107 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 107 Page - Renesas Technology Corp |
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107 / 577 page  7721 Group User’s Manual INTERRUPTS 7–10 7.5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 7.5.1 shows the interrupt priority level detection circuit. 7.5 Interrupt priority level detection circuit Fig. 7.5.1 Interrupt priority level detection circuit Interrupt with the highest priority level Interrupt priority level Level 0 (initial value) A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 IPL Processor interrupt priority level Interrupt disable flag (I) Watchdog timer interrupt Reset Accepting of interrupt request Interrupt priority level DMA1 DMA3 DMA2 DMA0 |
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