7721 datasheet(109/577 Pages) RENESAS

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7721 Group User’s Manual

INTERRUPTS

7–12

7.6 Interrupt priority level detection time

When the interrupt priority level detection time has passed after sampling starts, an interrupt request is

accepted. The interrupt priority level detection time can be selected by software. Figure 7.6.1 shows the

interrupt priority level detection time. Usually, select “2 cycles of

φ” as the interrupt priority level detection

time.

7.6 Interrupt priority level detection time

(2) Interrupt priority level detection time

Op-code fetch cycle

Sampling pulse

(a) 7 cycles

(b) 4 cycles

Interrupt priority level

detection time

(Note)

Note: The pulse resides when “2 cycles of

” is selected.

0 0

0 1

1 0

1 1

Processor mode register 0 (Address 5E16)

Processor mode bits

Software reset bit

Must be fixed to “0.”

Clock

output select bit

7 cycles of

[(a) shown below]

4 cycles of

[(b) shown below]

2 cycles of

[(c) shown below]

Interrupt priority detection time select bits

Do not select.

(1) Interrupt priority detection time select bits

b5, b4

Wait bit

Fig. 7.6.1 Interrupt priority level detection time

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