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7721 Datasheet(PDF) 224 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 224 Page - Renesas Technology Corp |
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224 / 577 page ![]() SERIAL I/O 7721 Group User’s Manual 11–21 11.3 Clock synchronous serial I/O mode 11.3.3 Transmit operation When the transmit conditions described in section “11.3.2 Method of transmission” are satisfied in the case of selecting an internal clock, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. When the transmit conditions are satisfied and the external clock is input to the CLKi pin in the case of selecting an external clock, the following operations are automatically performed. •The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. •The transmit buffer empty flag is set to “1.” •The transmit register empty flag is cleared to “0.” •8 transfer clocks are generated (when an internal clock is selected). •A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.” The transmit operations are described below: Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the falling edge of the transfer clock. This data is transmitted bit by bit sequentially beginning with the least significant bit. When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the completion of transmission. Figure 11.3.4 shows the transmit operation. When an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the transfer clock stops at “H” level. Figures 11.3.5 and 11.3.6 show examples of transmit timing. Fig. 11.3.4 Transmit operation Transfer clock UARTi transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 Transmit data MSB b7 b0 D0 D1 D2 D7 LSB UARTi transmit register |
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