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7721 Datasheet(PDF) 228 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 228 Page - Renesas Technology Corp |
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228 / 577 page  SERIAL I/O 7721 Group User’s Manual 11–25 11.3 Clock synchronous serial I/O mode Fig. 11.3.8 Initial setting example for relevant registers when receiving (2) Port P8 direction register (Address 1416) b7 b0 0 RXD0 pin 0 RXD1 pin From preceding Figure 11.3.7 UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Set dummy data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1 : Transmission enabled 1 1 Receive enable bit 1 : Reception enabled Reception starts. Note: Set the receive enable bit and the transmit enable bit to “1” simultaneously. |
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