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7721 Datasheet(PDF) 229 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 229 Page - Renesas Technology Corp |
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229 / 577 page  SERIAL I/O 7721 Group User’s Manual 11–26 11.3 Clock synchronous serial I/O mode Fig. 11.3.9 Processing after receive completion [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b7 b0 Reading of receive data Receive data is read out from here. b7 b0 Checking completion of reception 1 1 Note : This figure shows the bits and registers required for processing. Refer to “Figure 11.3.12” for the change of flag state and the occurrence timing of an interrupt request. b7 b0 Checking error 1 1 Overrun error flag 0: No overrun error 1: Overrun error detected UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Receive complete flag 0: Reception not completed 1: Reception completed |
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