7721 datasheet(220/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–17

11.3 Clock synchronous serial I/O mode

11.3.1 Transfer clock (Synchronizing clock)

Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select

whether to generate the transfer clock internally or to input it from the external.

The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing

only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register

in order to make the transmit control circuit active.

(1)

Internal generation of transfer clock

The count source selected with the BRG count source select bits is divided by the BRGi, and the

BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the

CLKi pin.

[Setting for relevant registers]

•Select an internal clock (bit 3 at addresses 3016, 3816 = “0”).

•Select the BRGi’s count source (bits 0 and 1 at addresses 3416, 3C16)

•Set “division value – 1” (= n; 0016 to FF16) to the BRGi (addresses 3116, 3916).

Transfer clock’s frequency =

•Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).

•Set data to the UARTi transmit buffer register (addresses 3216, 3A16)

[Pin’s state]

•A transfer clock is output from the CLKi pin.

•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)

(2)

Input of transfer clock from the external

A clock input from the CLKi pin is the transfer clock.

[Setting for relevant registers]

•Select an external clock (bit 3 at addresses 3016, 3816 = “1”).

•Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).

•Set data to the UARTi transmit buffer register (addresses 3216, 3A16).

[Pin’s state]

•A transfer clock is input from the CLKi pin.

•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)

fi: Frequency of BRGi’s count source (f2, f16, f64 , f512)

2 (n+1)

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