7721 datasheet(216/577 Pages) RENESAS

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SERIAL I/O

7721 Group User’s Manual

11–13

11.2.6 UARTi baud rate register (BRGi)

The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer

clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi

divides the count source frequency by (n + 1).

In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the

BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and

the BRGi’s output divided by 16 becomes the transfer clock.

The data which is written to the UARTi baud rate register (BRGi) is written to both the timer and the reload

performed while transmission/reception is stopped.

Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block

diagram of transfer clock generating section.

11.2 Block description

UART0 baud rate register (Address 3116)

UART1 baud rate register (Address 3916)

Functions

Bit

At reset

7 to 0

Can be set to “0016” to “FF16.”

Assuming that the set value = n, BRGi

divides the count source frequency by (n + 1).

Undefined

Note: Writing to this register must be performed while the transmission/reception halts.

Use the LDM or STA instruction for writing to this register.

Fig. 11.2.10 Structure of UARTi baud rate register (BRGi)

BRGi

1/2

Transmit control circuit

Receive control circuit

Transfer clock for transmit operation

Transfer clock for receive operation

Transmit control circuit

Receive control circuit

Transfer clock for transmit operation

Transfer clock for receive operation

BRGi

1/16

fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512)

fEXT : Clock input to CLKi pin (external clock)

1/16

fEXT

Fig. 11.2.11 Block diagram of transfer clock generating section

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