7721 datasheet(214/577 Pages) RENESAS

214 / 577 page

SERIAL I/O

7721 Group User’s Manual

11–11

11.2.5 UARTi receive register and UARTi receive buffer register

Figure 11.2.7 shows the block diagram for the receiver; Figure 11.2.8 shows the structure of UARTi receive

buffer register.

11.2 Block description

Fig. 11.2.7 Block diagram for receiver

Clock sync.

PAR

2SP

1SP

UART

RxDi

SP : Stop bit

PAR : Parity bit

8-bit UART

9-bit UART

7-bit UART

9-bit UART

Clock sync.

7-bit UART

8-bit UART

Data bus (even)

Data bus (odd)

UARTi receive register

Parity

enabled

Parity

disabled

UARTi receive

buffer register

Bit

8 to 0

At reset

Undefined

Functions

(b15)

(b8)

15 to 9

–

UART0 receive buffer register (Addresses 3716, 3616)

UART1 receive buffer register (Addresses 3F16, 3E16)

Nothing is assigned.

The value is “0” at reading.

Receive data is read out from here.

Fig. 11.2.8 Structure of UARTi receive buffer register

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