7721 datasheet(210/577 Pages) RENESAS

210 / 577 page

SERIAL I/O

7721 Group User’s Manual

11–7

11.2 Block description

11.2.3 UARTi transmit/receive control register 1

Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to

section “11.3.6 Processing on detecting overrun error” and “11.4.7 Processing on detecting error.”

Bit

Bit name

At reset

Framing error flag

(Valid in UART mode)

0 : No framing error

1 : Framing error detected

Functions

UART0 transmit/receive control register 1 (Address 3516)

UART1 transmit/receive control register 1 (Address 3D16)

Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial

I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.”

Bits 5 and 6 are cleared to “0” when one of the following is performed:

•Clearing the receive enable bit to “0”

•Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16)

out

•Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002”

Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.”

2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.

Transmit enable bit

0 : Transmission disabled

1 : Transmission enabled

Transmit buffer empty flag

0 : Data present in transmit buffer

1 : No data present in transmit

buffer register

Receive enable bit

0 : Reception disabled

1 : Reception enabled

Receive complete flag

0 : No data present in receive

buffer register

1 : Data present in receive buffer

Overrun error flag

0 : No overrun error

1 : Overrun error detected

Parity error flag

(Valid in UART mode)

0 : No parity error

1 : Parity error detected

Error sum flag

(Valid in UART mode)

0 : No error

1 : Error detected

(Notes 1, 2)

(Note 1)

Fig. 11.2.4 Structure of UARTi transmit/receive control register 1

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