7721 datasheet(212/577 Pages) RENESAS

212 / 577 page

SERIAL I/O

7721 Group User’s Manual

11–9

11.2.4 UARTi transmit register and UARTi transmit buffer register

Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi

transmit buffer register.

11.2 Block description

Fig. 11.2.5 Block diagram for transmitter

PAR

“0”

2SP

1SP

UART

7-bit UART

8-bit UART

7-bit UART

9-bit UART

Clock sync.

Data bus (even)

Data bus (odd)

TxDi

UARTi transmit register

Parity

enabled

Parity

disabled

SP : Stop bit

PAR : Parity bit

UARTi transmit

buffer register

8-bit UART

9-bit UART

Fig. 11.2.6 Structure of UARTi transmit buffer register

Bit

8 to 0

At reset

Undefined

Functions

(b15)

(b8)

15 to 9

–

Undefined

UART0 transmit buffer register (Addresses 3316, 3216)

UART1 transmit buffer register (Addresses 3B16, 3A16)

Nothing is assigned.

Transmit data is set.

Note: Use the LDM or STA instruction for writing to this register.

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