7721 datasheet(215/577 Pages) RENESAS

215 / 577 page

SERIAL I/O

7721 Group User’s Manual

11–12

The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data.

This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock.

The UARTi receive buffer register is used to read out receive data. When reception is completed, the

receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive

buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data

is ready in the UARTi receive register before the data which has been transferred to the UARTi receive

buffer register is read out. (i.e., an overrun error occurs.)

The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516,

3D16) to “1” after clearing it to “0.”

Figure 11.2.9 shows the contents of the UARTi receive buffer register when reception is completed.

11.2 Block description

000000

Receive data (9 bits)

Receive data (8 bits)

Receive data (7 bits)

In UART mode

(Transfer data length : 9 bits)

In clock synchronous

serial I/O mode

In UART mode

(Transfer data length : 8 bits)

In UART mode

(Transfer data length : 7 bits)

Same value as bit

7 in low-order byte

Same value as bit

6 in low-order byte

High-order byte

(addresses 3716, 3F16)

Low-order byte

(addresses 3616, 3E16)

Fig. 11.2.9 Contents of UARTi receive buffer register when reception is completed

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