Freescale Semiconductor

25

92

FST input (wl) to data out enable from high impedance

—

—

—

21.0

—

ns

93

FST input (wl) to transmitter #0 drive enable assertion

—

—

—

14.0

—

ns

94

Flag output valid after SCKT rising edge

—

—

—

—

14.0

9.0

x ck

i ck

ns

95

HCKR/HCKT clock cycle

—

2

10

—

—

ns

96

HCKT input rising edge to SCKT output

—

—

—

18.0

—

ns

97

HCKR input rising edge to SCKR output

—

—

—

18.0

—

ns

Note:

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

3. bl = bit length

wl = word length

wr = word length relative

4. SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7. Periodically sampled and not 100% tested.

8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.

Table 11. Enhanced Serial Audio Interface Timing (Continued)

No.

Min

Max