DSPB56725AF datasheet(14/48 Pages) FREESCALE

14 / 48 page

Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

1.2.1

Serial Host Interface SPI Protocol Timing

Table 9 lists the serial host interface SPI protocol timing.

Table 9. Serial Host Interface SPI Protocol Timing

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

Minimum serial clock cycle = tSPICC(min)

Master/Slave

Bypassed

× TC + 9

59.0

—

Very Narrow

× TC + 9

59.0

—

Narrow

× TC + 133

183.0

—

Wide

× TC + 333

383.0

—

Tolerable Spike width on data or clock in.

—

Bypassed

—

Very Narrow

—

Narrow

—

Wide

—

100

Serial clock high period

Master

Bypassed

0.5

× (tSPICC)

29.5

—

Very Narrow

0.5

× (tSPICC)

29.5

—

Narrow

0.5

× (tSPICC)

91.5

—

Wide

0.5

× (tSPICC)

191

—

Slave

Bypassed

2.5

× TC + 12

—

Very Narrow

2.5

× TC + 12

—

Narrow

2.5

× TC + 102

114.5

—

Wide

2.5

× TC + 189

201.5

—

Serial clock low period

Master

Bypassed

0.5

× (tSPICC)

29.5

—

Very Narrow

0.5

× (tSPICC)

29.5

—

Narrow

0.5

× (tSPICC)

91.5

—

Wide

0.5

× tSPICC)

191

—

Slave

Bypassed

2.5

× TC + 12

—

Very Narrow

2.5

× TC + 12

—

Narrow

2.5

× TC + 102

114.5

—

Wide

2.5

× TC + 189

201.5

—

Serial clock rise/fall time

Master

Slave

—

DSPB56725AF Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc

DSPB56725AF Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL