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DSPB56725AF Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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DSPB56725AF Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 48 page  Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 15 27 SS assertion to first SCK edge CPHA = 0 Slave Bypassed 3.5 × TC + 15 32.5 — ns Very Narrow 3.5 × TC + 5 22.5 — ns Narrow — 0 — ns Wide — 0 — ns CPHA = 1 Slave Bypassed — 10 — ns Very Narrow — 0 — ns Narrow — 0 — ns Wide — 0 — ns 28 Last SCK edge to SS not asserted Slave Bypassed — 12 — ns Very Narrow — 22 — ns Narrow — 100 — ns Wide — 200 — ns 29 Data input valid to SCK edge (data input set-up time) Master /Slave Bypassed — 0 — ns Very Narrow — 0 — ns Narrow — 0 — ns Wide — 0 — ns 30 SCK last sampling edge to data input not valid Master /Slave Bypassed 2 × TC + 10 20 — ns Very Narrow 2 × TC + 30 40 — ns Narrow 2 × TC + 60 70 — ns Wide — 100.0 — ns 31 SS assertion to data out active Slave — — 5 — ns 32 SS deassertion to data high impedance2 Slave — — — 9 ns 33 SCK edge to data out valid (data out delay time) Master /Slave Bypassed — — 46.2 ns Very Narrow — — 270 ns Narrow — — 376 ns Wide — — 521 ns 34 SCK edge to data out not valid (data out hold time) Master /Slave Bypassed — 11.67 — ns Very Narrow — 15 — ns Narrow — 55 — ns Wide — 105 — ns 35 SS assertion to data out valid (CPHA = 0) Slave — — — 14.0 ns Table 9. Serial Host Interface SPI Protocol Timing (Continued) No. Characteristics1,3,4 Mode Filter Mode Expression Min Max Unit |
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