DSPB56725AF datasheet(29/48 Pages) FREESCALE

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Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

Figure 21 shows the GPIO timing diagram.

Figure 21. GPIO Timing

1.2.6

JTAG Timing

Table 13 lists the JTAG timing.

Table 13. JTAG Timing

No.

Characteristics

All Frequencies

Unit

Min

Max

108

TCK frequency of operation (1/(TC × 3); maximum 10 MHz)

—

10.0

MHz

109

TCK cycle time in Crystal mode

100.0

—

110

TCK clock pulse width measured at 1.65 V

50.0

—

111

TCK rise and fall times

—

3.0

112

Boundary scan input data setup time

15.0

—

113

Boundary scan input data hold time

24.0

—

114

TCK low to output data valid

—

40.0

115

TCK low to output high impedance

—

40.0

116

TMS, TDI data setup time

5.0

—

117

TMS, TDI data hold time

25.0

—

118

TCK low to TDO data valid

—

44.0

119

TCK low to TDO high impedance

—

44.0

Note:

1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100° C, CL = 50 pF

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

GPIO

(Input)

GPIO

(Output)

Fsys

100

101

102

103

GPIO

(Output)

104

105

106

107

Valid

DSPB56725AF Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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