DSPB56725AF datasheet(45/48 Pages) FREESCALE

45 / 48 page

Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

Product Documentation

Table 21 lists the documents that provide a complete description of the DSP56724/DSP56725 devices and are required to design

properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor,

semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source

for the latest information).

Revision History

Table 22 summarizes revisions to this document.

Table 21. DSP56724 / DSP56725 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56300-family architecture and the 24-bit

core processor and instruction set

DSP56300FM

DSP56724/DSP56725 Reference Manual Detailed description of memory, peripherals, and interfaces

DSP56724RM

DSP56724 Product Brief

Brief description of the DSP56724 device

DSP56724PB

DSP56725 Product Brief

Brief description of the DSP56725 device

DSP56725PB

DSP56724/DSP56725 Data Sheet

Electrical and timing specifications; pin and package descriptions

(this document)

DSP56724

Table 22. Revision History

Revision

Date

Description

12/2008

• Modified values and removed rows in Table 4, “DC Electrical Characteristics.”

• Removed “IO_VDD_25” from Figure 4, “Prevent High Current Conditions by Applying

IO_VDD Before Core_VDD.”

•In Table 7, “Reset, Stop, Mode Select, and Interrupt Timing,” for No. 15, changed 10 to

12, and for No. 16, changed 4 to 7.

•In Table 9, “Serial Host Interface SPI Protocol Timing,” updated values.

•In Table 10, “SHI I2C Protocol Timing,” added note 7 and changed Max values for No. 50

to 1000 and 300; in addition, updated the values for note 1.

•In Table 11, “Enhanced Serial Audio Interface Timing,” for No. 82, changed 19 to 15; for

No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25.

• Removed Section 1.2.5, “Timer Timing.”

•In Table 16, “EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2),” for

“LSYNC_IN (except LGTA/LUPWAIT),” changed 2 to 3.

•In Table 17, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4),” for

“LCLK to output high impedance for LAD [23:0],” changed 9 to 8.1.

•In Table 18, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8),” for

LCLK to output high impedance for LAD [23:0],” changed 19 to 17.1

•In Table 19, “Ordering Information,” added rows for DSPB56724CAG and

DSPB56725CAF, and changed “DSPA56724AG” to “DSPB56724AG.”

6/2008

• Initial public release.

DSPB56725AF Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc

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